9 個結果

相關度 | 價格低到高 | 價格高到低
  1. ASIC DESIGN AND SYNTHESIS: RTL DESIGN USING VERILOG

    ASIC DESIGN AND SYNTHESIS: RTL DESIGN USING VERILOG

    11,999

    博客來

  2. ASIC DESIGN AND SYNTHESIS: RTL DESIGN USING VERILOG

    ASIC DESIGN AND SYNTHESIS: RTL DESIGN USING VERILOG

    8,399

    博客來

  3. DIGITAL LOGIC DESIGN USING VERILOG: CODING AND RTL SYNTHESIS

    DIGITAL LOGIC DESIGN USING VERILOG: CODING AND RTL SYNTHESIS

    7,799

    博客來

  4. DIGITAL LOGIC DESIGN USING VERILOG: CODING AND RTL SYNTHESIS

    DIGITAL LOGIC DESIGN USING VERILOG: CODING AND RTL SYNTHESIS

    5,999

    博客來

  5. DIGITAL LOGIC DESIGN USING VERILOG: CODING AND RTL SYNTHESIS

    DIGITAL LOGIC DESIGN USING VERILOG: CODING AND RTL SYNTHESIS

    8,399

    博客來

  6. ADVANCED HDL SYNTHESIS AND SOC PROTOTYPING: RTL DESIGN USING VERILOG

    ADVANCED HDL SYNTHESIS AND SOC PROTOTYPING: RTL DESIGN USING VERILOG

    11,999

    博客來

  7. PRINCIPLES OF VERIFIABLE RTL DESIGN: A FUNCTIONAL CODING STYLE SUPPORTING VERIFICATION PROCESSES IN VERILOG

    PRINCIPLES OF VERIFIABLE RTL DESIGN: A FUNCTIONAL CODING STYLE SUPPORTING VERIFICATION PROCESSES IN VERILOG

    11,000

    博客來

  8. PRINCIPLES OF VERIFIABLE RTL DESIGN: A FUNCTIONAL CODING STYLE SUPPORTING VERIFICATION PROCESSES IN VERILOG

    PRINCIPLES OF VERIFIABLE RTL DESIGN: A FUNCTIONAL CODING STYLE SUPPORTING VERIFICATION PROCESSES IN VERILOG

    6,599

    博客來

  9. DIGITAL DESIGN WITH RTL DESIGN, VHDL, AND VERILOG 2ND

    DIGITAL DESIGN WITH RTL DESIGN, VHDL, AND VERILOG 2ND

    399

    蝦皮購物